1. Field of the Invention
The present invention relates to the formation of integrated circuits, and, more particularly, to the formation of field effect transistors having a channel region with a specified intrinsic stress to improve the charge carrier mobility.
2. Description of the Related Art
Integrated circuits comprise a large number of individual circuit elements such as, e.g., transistors, capacitors and resistors. These elements are connected internally to form complex circuits such as memory devices, logic devices and microprocessors. The performance of integrated circuits can be improved by increasing the number of functional elements in the circuit in order to increase their functionality and/or by increasing the speed of operation of the circuit elements. A reduction of feature sizes allows the formation of a greater number of circuit elements on the same area, hence allowing an extension of the functionality of the circuit, and also reduces signal propagation delays, thus making an increase of the speed of operation of circuit elements possible.
Field effect transistors are used as switching elements in integrated circuits. They allow control of current flowing through a channel region located between a source region and a drain region. The source region and the drain region are highly doped. In N-type transistors, the source and drain regions are doped with an N-type dopant. Conversely, in P-type transistors, the source and drain regions are doped with a P-type dopant. The doping of the channel region is inverse to the doping of the source region and the drain region. The conductivity of the channel region is controlled by a gate voltage applied to a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. Depending on the gate voltage, the channel region may be switched between a conductive “on” state and a substantially non-conductive “off” state.
The source region, the drain region and the gate electrode of a field effect transistor in an integrated circuit are connected to other circuit elements by means of contact vias which are formed in a layer of an interlayer dielectric over the transistor. Since the source and drain regions and the gate electrode have different heights, and a surface of the interlayer dielectric is substantially planar, the individual contact vias have different depths. In the formation of the contact vias, a mask is formed on the interlayer dielectric which exposes those portions of the interlayer dielectric where the contact vias are to be formed. Then, an anisotropic etching process is performed. In order to avoid that an etchant used in the etching process affects the transistor, an etch stop layer is provided between the transistor and the interlayer dielectric. The etchant is adapted to selectively remove the interlayer dielectric, leaving a material of the etch stop layer substantially intact. Thus, the etching stops as soon as the etch front reaches the etch stop layer, irrespective of the height of the feature below the contact via.
When reducing the size of field effect transistors, it is important to maintain a high conductivity of the channel region in the “on” state. The conductivity of the channel region in the “on” state depends on the dopant concentration in the channel region, the mobility of the charge carriers, the extension of the channel region in the width direction of the transistor and the distance between the source region and the drain region, which is commonly denoted as “channel length.” While a reduction of the width of the channel region leads to a decrease of the channel conductivity, a reduction of the channel length enhances the channel conductivity. An increase of the charge carrier mobility leads to an increase of the channel conductivity.
As feature sizes are reduced, the extension of the channel region in the width direction is also reduced. A reduction of the channel length entails a plurality of issues associated therewith. First, advanced techniques of photolithography and etching have to be provided in order to reliably and reproducibly create transistors having short channel lengths. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the source region and in the drain region in order to provide a low sheet resistivity and a low contact resistivity in combination with a desired channel controllability. Furthermore, a reduction of the channel length may entail a need to reduce the depth of the source region and the drain region with respect to the interface formed by the gate insulation layer and the channel region which may, in some approaches, be achieved by forming raised source and drain regions formed with a specified offset to the gate electrode.
In view of the problems associated with a further reduction of the channel length, it has been proposed to also enhance the performance of field effect transistors by increasing the charge carrier mobility in the channel region. In principle, at least two approaches may be used to increase the charge carrier mobility.
First, the dopant concentration in the channel region may be reduced. Thus, the probability of scattering events of charge carriers in the channel region is reduced, which leads to an increase of the conductivity of the channel region. Reducing the dopant concentration in the channel region, however, significantly affects the threshold voltage of the transistor device. This makes the reduction of dopant concentration a less attractive approach.
Second, the lattice structure in the channel region may be modified by creating tensile or compressive stress. This leads to a modified mobility of electrons and holes, respectively. A tensile stress in the channel region increases the mobility of electrons. Depending on the magnitude of the tensile stress, an increase of the electron mobility of up to 20% or more can be achieved. In an N-type transistor, this leads to a corresponding increase of the conductivity of the channel region. Conversely, compressive stress in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
In a method of forming field effect transistors having stressed channel regions according to the state of the art, a layer comprising an alloy of silicon and germanium or an alloy of silicon and carbon, respectively, is introduced into the channel region in order to create a tensile or compressive stress. Alternatively, such a stress-creating layer may be provided below the channel region.
A problem of the method of forming field effect transistors having stressed channel regions according to the state of the art is that the formation of the stress-creating layer requires a considerable modification of conventional and well-approved techniques used for the formation of field effect transistors. For instance, additional epitaxial growth techniques have to be developed and implemented into the process flow in order to form the stress-creating layers. Thus, the complexity of the formation of the transistors is significantly increased compared to the formation of transistors without stress-creating layers in or below the channel region.
In view of the above problem, a need exists for a method allowing creation of desired stress conditions in a field effect transistor without requiring substantial modifications of the manufacturing process.